![]() The LEDs used are current limited using 220Ohm resistor. Thus, the initial state according to the truth table is as shown above. Hence, default input state will be LOW across all the pins except R which is state of normal operation. The pins J, K, CLK are normally pulled down and pin R is pulled up. Thus, for different input at D the corresponding output can be seen through LED Q and Q’. Hence, the regulated 5V output is used as the Vcc and pin supply to the IC. The 9V battery acts as the input to the voltage regulator LM7805. The two LEDs Q and Q’ represents the output states of the flip-flop. The buttons J(Data1), K(Data2), R(Reset), CLK(Clock) are the inputs for the JK flip-flop. Practical Demonstration and Working of JK Flip-Flop: We have used a LM7805 regulator to limit the LED voltage. Also we have used LED at output, the source has been limited to 5V to control the supply voltage and DC output voltage. The IC power source V DD ranges from 0 to +7V and the data is available in the datasheet. ![]() JK Flip-flop Circuit diagram and Explanation: IC MC74HC73A (Dual JK flip-flop) – 1No.Above is the pin diagram and the corresponding description of the pins. It is a 14 pin package which contains 2 individual JK flip-flop inside. The IC used is MC74HC73A (Dual JK-type flip-flop with RESET). Hence, this pin always pulled up and can be pulled down only when needed. All the pins will become inactive upon LOW at RESET pin. Analysing the above assembly as a two stage structure considering previous state (Q’) to be 0 Thus, comparing the three input and two input NAND gate truth table and applying the inputs as given in JK flip-flop truth table the output can be analysed. Representation of JK Flip-Flop using Logic Gates: This, works like SR flip-flop for the complimentary inputs and the advantage is that this has toggling function. But, the important thing to consider is all these can occur only in the presence of the clock signal. According to the table, based on the inputs, the output changes its state. The Q and Q’ represents the output states of the flip-flop. The J (Jack) and K (Kilby) are the input states for the JK flip-flop. Thus, the output has two stable states based on the inputs which have been discussed below. Thus, JK flip-flop is a controlled Bi-stable latch where the clock signal is the control signal. The clock has to be high for the inputs to get active. Whenever the clock signal is LOW, the input is never going to affect the output state. Hence they are mostly used in counters and PWM generation, etc. Here we are using NAND gates for demonstrating the JK flip flop Inspite of the simple wiring of D type flip-flop, JK flip-flop has a toggling nature. The major applications of JK flip-flop are Shift registers, storage registers, counters and control circuits. Due to its versatility they are available as IC packages. The name JK flip-flop is termed from the inventor Jack Kilby from texas instruments. Here in this article we will discuss about JK Flip Flop. ![]() Out of the above types only JK and D flip-flops are available in the integrated IC form and also used widely in most of the applications. ![]()
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